1. Field of the Invention
The present invention relates to semiconductor devices and in particular to semiconductor devices with an antifuse having a resistance value reduced when it is blown.
2. Description of the Background Art
FIG. 18 is a block diagram showing a configuration of a conventional dynamic random access memory (DRAM) 30. Referring to FIG. 18, DRAM 30 includes a clock generation circuit 31, a row and column address buffer 32, a row decoder 33, a column decoder 34, a redundant column decoder 35, a memory mat 36, an input buffer 40 and an output buffer 41, memory mat 36 including a memory array 37, a redundant memory array 38 and a sense amplifier+input/output control circuit 39.
Clock generation circuit 31 responds to externally applied signals /RAS and /CAS to select a predetermined mode of operation to generally control DRAM 30.
Row and column address buffer 32 responds to address signals A0 to An, n representing an integer no less than 0, to generate row address signals RA0 to RAn and column address signals CA0 to CAn for supply to row decoder 33 and column decoders 34 and 35, respectively.
Memory array 37 includes a plurality of memory cells arranged in a matrix, each storing 1-bit data. Each memory cell is arranged at a predetermined address determined according to row and column addresses.
Row decoder 33 responds to row address signals RA0 to RAn from row and column address buffer 32 to designate a row address in memory array 37. Column decoder 34 responds to column address signals CA0 to CAn from row and column address buffer 32 to designate a column address in memory array 37.
In column decoder 34 and redundant column decoder 35 is provided a group of fuses (not shown) for programming a column address of memory array 37 that includes a defective memory cell and a column address of a redundant memory array 35 that replaces the column address including the defective memory cell. When column address signals CA0 to CAn are input that correspond to a defective column address programmed by the group of fuses, column decoder 34 does not designate the column address and redundant column decoder 35 designates a programmed column address of redundant memory array 38 rather than the defective column address. Thus, a defective memory cell column in memory array 37 that includes a defective memory cell is replaced by a normal memory cell column of redundant memory array 38.
Sense amplifier+input/output control circuit 39 connects a memory cell of an address designated by row decoder 33 and column decoder 34 (or redundant column decoder 35) to one end of a data input/output line pair IOP. The other end of data input/output line pair IOP is connected to input and output buffers 40 and 41. Input buffer 40 responds to an externally applied signal /W in a write mode to supply externally input data to a selected memory cell via data input/output line pair IOP. Output buffer 41 responds to an externally input signal /OE in a read mode to externally output data read from a selected memory cell.
FIG. 19 is a circuit block diagram showing a partially omitted configuration of the FIG. 18 DRAM memory mat 36.
Referring to FIG. 19, memory array 37 includes a plurality of memory cells MC arranged in a matrix, a word line WL corresponding to each row, and a pair of bit lines BL, /BL corresponding to each column.
Each memory cell MC is of a well-known type, including an n-channel MOS transistor for access and a capacitor for storage of information. Word line WL transmits an output from row decoder 33 to activate memory cells MC of a selected row. The pair of bit lines BL, /BL inputs and outputs a data signal to and from a selected memory cell MC.
Redundant memory array 38 is similar in configuration to memory array 37, except that it is smaller than memory array 37 in the number of columns. Memory array 37 and redundant memory array 38 have the same number of rows and share word line WL.
Sense amplifier+input/output control circuit 39 includes a column select gate 42, a sense amplifier 34 and an equalizer 44, each provided for a respective column. Column select gate 42 includes a pair of n-channel MOS transistors connected between the pair of bit lines BL, /BL and a pair of data input and output lines IO, /IO. The gate of each n-channel MOS transistor is connected to column decoder 34 or 35 via a column select line CSL. When column decoder 34 or 35 causes column select line CSL to attain a selected high level, the pair of n-channel MOS transistors are turned on to couple the pair of bit lines BL, /BL and the pair of data input and output lines IO,/IO together.
Sense amplifier 43 amplifies a fine difference in potential between paired bit lines BL and /BL to a power supply voltage Vcc when sense amplifier activation signals SE and /SE respectively attain high and low levels. Equalizer 44 equalizes the potentials of bit lines BL, /BL to a bit line potential VBL=Vcc/2 when a bit line equalization signal BLEQ attains an active high level.
An operation of the FIGS. 18 and 19 DRAM will now be described briefly. In a write mode, column decoder 34 or 35 allows column select line CSL of a column corresponding to column address signals CA0-CAn to attain a high level to turn on column select gate 42.
Input buffer 40 responds to signal /W to supply external write data to the pair of bit lines BL, /BL of the selected column via data input/output line pair IOP. The write data is supplied as a potential difference between bit lines BL and /BL. Then, row decoder 33 allows word line WL of a row corresponding to row address signals RA0-RAn to attain an active high level to turn on the n-channel MOS transistors of memory cells MC of the row. The capacitor of a selected memory cells MC stores the amount of electrical charge that corresponds to the potential of bit line BL or /BL.
In a read mode, bit line equalization signal BLEQ initially falls to a low level to stop equalization of bit lines BL and /BL. Row decoder 33 allows word line WL of a row corresponding to row address signals RA0-RAn to attain a selected high level. The potentials of bit lines BL and /BL slightly vary depending on the amount of electrical charge in the capacitor of an activated memory cell MC.
Then, sense amplifier activation signals SE and /SE attain high and low levels, respectively, to activate sense amplifier 43. When the potential of bit line BL is slightly higher than that of bit line /BL, the potential of bit line BL is pulled up to a high level and that of bit line /BL is pulled down to a low level. When the potential of bit line /BL is slightly higher than that of bit line BL, the potential of bit line /BL is pulled up to a high level and that of bit line BL is pulled down to a low level.
Then, column decoder 34 or 35 allows column select line CSL of a column corresponding to column address signals CA0-CAn to attain a selected high level to turn on column select gate 42 of the column. The data of bit line pair BL, /BL of the selected column is supplied to output buffer 41 via column select gate 42 and the pair of data input and output lines IO, /IO. Output buffer 41 responds to a signal /OE to externally output read data.
If column address signals CA0-CAn correspond to a column including any defective memory cell MC, the write and read operations are performed similarly, except that a column of redundant memory array 38 is selected in place of the column including the defective memory cell MC.
Thus in memory integrated circuits such as DRAM the system of replacing defective rows and columns with spare rows and columns are adopted and a program circuit for previously programming addresses of defective rows and columns is provided to increase the ratio of satisfactory chips on a wafer.
FIG. 20 is a circuit diagram showing a configuration of such program circuits as described above. One such program circuit is disclosed e.g. in IEEE Journal of Solid-State Circuits, Vol. SC-18(1983), pp. 441-446.
The program circuit shown in FIG. 20 includes a p-channel MOS transistor 51, fuses 50. 0-50.n, 52. 0'-52.n', and n-channel MOS transistors 53. 0-53.n, 53.0-53.n'. P-channel MOS transistor 51 is connected between a line of a power supply potential Vcc and output node N51 and has its gate receiving a signal RP.
Fuse 52.0 and n-channel MOS transistor 53.0 are provided for address signal A0 (i.e. a row address signal RA0 or a column address signal CA0) and connected in series between output node N51 and a line of ground potential GND. Fuse 52.0' and n-channel MOS transistor 53.0' are provided for a signal /A0 complementary to address signal A0 and connected in series between output node N51 and a line of ground potential GND. N-channel MOS transistors 53.0, 53.0' have their respective gates receiving signals A0, /A0, respectively. It should be noted that complementary address signal /A0 is generated in a row and column address buffer or decoder. Other fuses 52.1-52.n, 52.1'-52.n, and n-channel MOS transistors 52.1-52.n, 52.1'-52.n' are similar. Fuses 52.0-52.n, 52.0-52.n' are formed from polysilicon wire or aluminum wire. A potential of output node N51 serves as an output signal .phi.DA.
A defective address is programmed by laser-cutting a fuse corresponding to the defective address. When an input address matches a programmed defective address, a non-conducting state is achieved between output node N51 and a line of ground potential GND and, in response to signal RP that goes low, signal .phi.DA goes high. Responsively, a defective row or column is replaced by a spare row or column.
When an input address does not match a programmed defective address, a conducting state is achieved between output node N51 and a line of ground potential GND, and signal .phi.DA remains low even when signal RP goes low. Thus, replacement of rows or columns is not performed.
However, the program circuit shown in FIG. 20, using a laser device to cut fuses, requires high device cost and is poor in the precision of fuse-cutting.
Thus, consideration has been given to a program circuit with antifuses, which dispenses with a laser device. The antifuse has a capasitive structure, serving as a capacitor or an open circuit when it is intact. However, when a high voltage (of approximately no less than 10V) is applied thereto to blow it, a conductive path is created in the insulation layer to render the antifuse a resistance element having a resistance value of approximately several k.OMEGA..
FIG. 21 is a circuit diagram showing a configuration of a fuse circuit including such an antifuse and a blow circuit therefor. Such a fuse circuit is disclosed e.g. in U.S. Pat. No. 5,631,862.
The fuse circuit shown in FIG. 21 includes an antifuse 61, p-channel MOS transistors 62-64, n-channel MOS transistors 65-69, and an inverter 70. MOS transistors 62, 64, 65 are connected in series between a power supply potential Vcc line and a node N65. P-channel MOS transistor 62 has its gate receiving a signal TRAS. Signal TRAS is a trigger signal which is held low during address detection period and is otherwise held high.
P-channel MOS transistor 64 has its gate connected to a ground potential GND line so that transistor 64 is normally turned on. The channel length and channel width of p-channel MOS transistor 64 is designed such that p-channel MOS transistor 65 has a conduction resistance value of approximately 300k.OMEGA.. N-channel MOS transistor 65 has its gate receiving a signal DVCE. Signal DVCE is a signal enabling the fuse circuit, adapted to be half the level of power supply potential Vcc, i.e. Vcc/2, in blowing antifuse 61 and in detecting an address. The channel length and channel width of n-channel MOS transistor 65 is set such that the voltage driving capability of n-channel MOS transistor 65 is greater than that of p-channel MOS transistor 64.
Inverter 70 is connected between a node N64 between MOS transistors 64 and 65, and the gate of p-channel MOS transistor 63. A signal output from inverter 70 serves as an output signal FR of the fuse circuit. Signal FR serves as a signal input to an NOR- or NAND-type address comparator circuit for comparing an input address signal to a programmed address signal ADDR.
N-channel MOS transistor 66 is connected between node N65 and a ground potential GND line and has its gate receiving a reset signal RST. Reset signal RST is set high in setting an initial state of the fuse circuit. N-channel MOS transistors 67, 68 are connected in series between node N65 and a ground potential GND line and have their respective gates receiving address signal ADDR and signal FR, respectively.
N-channel MOS transistor 69 is connected between node N65 and one electrode of antifuse 61 and has its gate connected to a power supply potential Vcc line. In blowing antifuse 61, n-channel MOS transistor 69 prevents n-channel MOS transistors 65-67 from receiving between their respective sources and gates or their respective drains and gates a voltage of no less than the breakdown voltage of the gate oxide film to protect n-channel MOS transistors 65-67.
The other electrode of antifuse 61 is connected a terminal T61. Terminal T61 receives ground potential GND in a normal mode of operation and receives a high voltage in blowing antifuse 61.
An operation of the fuse circuit will now be described. To program a defective address, signal TRAS is initially set high and signal RST is raised high to set nodes N64, N65 low and signal FR is raised high before signal RST is returned low.
Then, address signal ADDR corresponding to the effective address is set high and one electrode of antifuse 61 is grounded via n-channel MOS transistors 69, 67, 68. Then, the high voltage is applied to terminal T61 to blow antifuse 61.
When antifuse 61 is blown, current flows from terminal T61 via antifuse 61 and n-channel MOS transistors 69, 67, 68 to the ground potential GND line and as the current increases the potentials of nodes N64, N65 are also increased. When the node N64 potential exceeds the logical threshold voltage of inverter 70, signal FR goes low and n-channel MOS transistor 68 is thus turned off to shut the current path to the ground potential GND line. This prevents excessively large current from flowing through the circuit when antifuse 61 is blown.
In the normal mode of operation, terminal T61 is grounded and signal TRAS goes low. When antifuse 61 is unblown, nodes N64, N65 go high and signal FR is latched low.
When antifuse 61 is blown, it serves as a resistance element of several k.OMEGA. and node N65 thus attains ground potential GND. Since n-channel MOS transistor 65 is greater in current driving capability than p-channel MOS transistor 64, the node N64 potential is lower than the logical threshold potential of inverter 70 and signal FR thus goes high. When an address is input that corresponds to an address detection circuit block with signal FR high, determination is made that a defective address has been input and the corresponding defective row or column is substituted by a spare row or column.
However, the conventional fuse circuit using an externally applied high voltage to blow antifuse 61 requires a protection circuit for preventing excessive current from flowing through the circuit when the antifuse 61 resistance value is decreased and it also requires separately a control circuit for controlling the externally applied high voltage, disadvantageously resulting in increasing the scale of the circuit.